Field
Embodiments described herein generally relate to methods for forming a semiconductor device having an air gap. More specifically, embodiments described herein relate to an air gap interconnect formed by utilizing an ion implantation process along with an etching process
Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The demand for greater circuit density necessitates a reduction in the dimensions of the integrated circuit components, e.g., sub-micron dimensions and the use of various materials to fabricate devices in order to achieve much faster and better electrical performance, such as materials with higher conductivity used to form metal lines, materials with lower permittivity (low-k) dielectric constant used as an insulating layer, etc.
For integrated circuit fabrication, metal interconnects with low resistance, such as copper and aluminum interconnects, provide conductive paths between the integrated circuit components on integrated circuit devices. Generally, metal interconnects are electrically isolated from each other by a dielectric bulk insulating material. At sub-micron dimensions, capacitive coupling potentially occurs between adjacent metal interconnects, which may cause cross talk and/or resistance-capacitance (RC) delay and degrade the overall performance of the integrated circuit.
One method for forming vertical and horizontal interconnects for the integrated circuit is by a damascene or dual damascene method. Typically, damascene structures have dielectric bulk insulating layers and conductive metal layers, such as low dielectric constant materials (dielectric constant less than 4) and conductive copper layers, stacked on top of one another. Vertical interconnects, i.e., vias, and horizontal interconnects, i.e., trenches, are etched into the dielectric bulk insulating layer and the conductive metal wirings are subsequently filled into the vias and/or trenches and planarized, such as by a chemical mechanical planarization process (CMP), so that the conductive metal wirings are only left in the vias and/or trenches. In the damascene approach, a rather complex dielectric film stack that includes a sequence of hard mask, low-k dielectrics, etch stop layers, air gaps, etc., may be required.
Given the scaling performance limitations of conventional low-k materials in lowering the dielectric constant (k) as a result of compromising mechanical strength and current leakage performance, one promising candidate for capacitance scaling includes the adoption of air gaps between metal wiring. Air gaps, which have a k value near 1.0, help reduce the overall effective k value to acceptable levels within the device.
However, conventional deposition processes for forming an air gap in the interconnection structure often has poor dimension, size and profile control. For example, in the exemplary interconnection structure 100 depicted in FIG. 1, the interconnection structure 100 includes air gaps 114 formed in a first low-k insulating material 106 disposed on a second low-k insulating material 104 formed on a substrate 102. Conductive metal wirings 108 may be formed between the first and the second low-k insulating materials 106, 104.
As the conventional plasma enhanced chemical vapor deposition (PECVD) process utilized to form the air gaps 114 in the interconnection structure 100 may have different step-coverage (e.g., conformality) at different locations or different degrees of overhang at the corners of the vias while filling the first low-k insulating material 106 among the metal wirings 108, the resultant air gaps 114 formed within the first low-k insulating material 106 may have varying and unpredictable dimensions 110, 112, thus resulting in unreliable or unpredictable electrical performance of the integrated circuit.
Thus, there is a need for improved methods for forming air gaps in insulating materials of interconnection structures for integrated circuits having more reliable and predictable geometry.